Keynotes

October 7, 2013, Monday, Dr. Sani Nassif, IEEE Fellow and IBM Master Inventor, IBM Austin Research Lab

VLSI 2.0: R&D Post Moore
The semiconductor industry has largely gotten off the Moore’s law treadmill. Many companies have stopped scaling, realizing that the 65, 45 or 32nm are sufficient for their needs, and relying on foundries to shoulder the risk and capital requirements for advanced nodes. This has resulted in a reduced need for VLSI-oriented research as the industry consolidates and traditional funding sources ramp down. So what does a VLSI researcher do then? Well she or he finds interesting problems to solve in so-called “adjacent” areas. But how does one get started, and how does one find such interesting research areas? This keynote is about two such examples… from VLSI to Proton Radiation Therapy and to Energy Distribution Optimization. It turns out that there are abundant opportunities for those willing to take risks and learn new things. Humanity has invested over $1T in semiconductor R&D, it is time to take that investment and apply its results more broadly!


October 8, 2013, Tuesday, Prof. Yale Patt, IEEE and ACM Fellow, University of Texas Austin

The Run-time System: Part of the operating system or part of the chip design?
My main mantra for quite a long time has been that if microprocessors are to continue to achieve higher and higher levels of performance, particularly in the current era of energy efficiency and multicore, we need to break the artificial barriers between the various abstraction layers that applications undergo between the statement of the problem in natural language and the electrons that do the actual work. Unfortunately, breaking those layers takes people out of their comfort zones. Nonetheless, we have succeeded in a very limited way to break some of those layers, and it has paid off. In this talk I hope to describe the transformation hierarchy, describe some of the artificial barriers and the benefits that could come from breaking those barriers, and discuss what we have to do to break them. Importantly, multicore provides a unique opportunity, and I will discuss what must be done if we are to place the run-time system where belongs in the hierarchy, i.e., as part of the chip design.


October 9, 2013, Wednesday, Dr. Magdy Abadir, IEEE Fellow and Director, Freescale

Data Mining Trends in VLSI Test
This talk will review several key challenges in design automation in areas such as pre-silicon functional verification, design-silicon debug, test cost reduction and quality improvement. We will describe data mining technologies to implement a prediction platform that provides unique solutions to cover these challenges. In the functional verification space, we will demonstrate an iterative learning framework for reducing simulation costs and improving coverage. In design-silicon debug, we will show a framework for analyzing design and test data for extracting knowledge that explains unexpected timing miss correlation results. This framework has been successfully used to debug early silicon design issues. In the manufacturing test space, we will show two different test analysis frameworks for reducing test cost and improve test quality. The first framework will demonstrate the ability to find predictive models to predict parts that are likely-to-fail during burn-in. The second framework will demonstrate the ability to learn from the wafer test data of known customer returns and apply these models to screen parts that may lead to field failures in the future.